The present invention relates to a pulse width modulation system for controlling a pulse width modulation of a pulse width modulation circuit, and an image forming apparatus having the pulse width modulation system and forming images.
In the prior art, an image output onto a recording medium (e.g. paper) by a digital copying machine comprises lattice-like divided fine points (dots), as shown in FIG. 1A. Each dot is called a pixel. Normally, one pixel is input in synchronism with one cycle T of an image transfer clock, as shown in FIG. 2A. In this case, one pixel is either all-black (indicated by A in FIG. 1A) or all-white (indicated by B in FIG. 1A). For example, where an image xe2x80x9cAxe2x80x9d is printed out on a recording medium (e.g. paper), it becomes as shown in FIG. 1A.
It is understood, however, that the image quality of image xe2x80x9cAxe2x80x9d is enhanced, as shown in FIG. 1B, if the pixel is not limited to all-black or all-white and, for example, the pixel is provided with two information items, i.e. density, such as half-black, and a print start position.
In general terms, a higher image quality is a most desired requirement for digital copying machines. In a laser modulation section of a conventional digital copying machine, a pulse width modulation is carried out in order to meet the above requirement and enhance the image quality. This technique has two functions. One is to control the density of the pixel by providing the all-black or all-white pixel with light emission time information for decreasing or increasing a laser emission time. The other is to control a print start position by providing light emission position information for shifting the laser emission position to the left or to the right. From these functions, pixels having the two information items are generated to enhance the image quality.
The pulse width modulation will now be described in greater detail.
Normally, in the pulse width modulation, in order to control the laser emission time, a one-cycle (two-division cycle) signal of the input signal (image transfer clock) is subjected to a division control and n-division pulse width modulation signals are formed. Thereby, image data with n+1 kinds of densities is generated.
Specifically, this means that n+1 kinds (0/n, 1/n, 2/n, . . . (nxe2x88x921)/n, n/n) of pixels are generated from one kind (all-black) of pixel. The density of each pixel to be printed is controlled by a pulse width. In this context, the (0/n) pixel is the all-white pixel, and the (n/n) pixel is the all-black pixel.
Moreover, not only the pulse width but also the print start position, i.e. pulse start position, is controlled at the same time in order to control the laser emission position. Thereby, a higher image quality can be obtained.
An example of a technique for obtaining a higher image quality will further be described in detail.
FIGS. 2A and 2B illustrate a 4-division pulse width modulation in association with waveform data and pixels. FIGS. 1A to 1C show an actual example of the 4-division pulse width modulation in which a 4-division pulse width conversion is made from Kdpi to 4 Kdpi in the main scan direction. In this case, K is a given integer. If K=100, for instance, a pulse width conversion is performed from 100 dpi to 400 dpi.
Assume that in FIGS. 1A to 1C an image xe2x80x9cAxe2x80x9d is printed and output on a recording medium (e.g. paper). If image data is represented by only all-black (A in the Figure) or all-white (B in the Figure) with Kdpi in FIG. 1A, jaggy becomes conspicuous around the character xe2x80x9cAxe2x80x9d and the image becomes rough.
In FIG. 1B, however, 4-division pulse width modulation signals are formed with 4 Kdpi. Thereby, pixels with five kinds of densities (0/4, 1/4, 2/4, 3/4, 4/4 pixels) are generated. Moreover, by controlling the pulse start position, eight kinds of pixels are generated. Since the 0/4 pixel and 4/4 pixel have no distinction between the right and left, eight kinds of pixels are obtained: 0/4 pixel, left 1/4 pixel, left 2/4 pixel, left 3/4 pixel, right 1/4 pixel, right 2/4 pixel, right 3/4 pixel, and 4/4 pixel. Accordingly, the character xe2x80x9cAxe2x80x9d is expressed by the combinations of the eight kinds of pixels. As a result, peripheral shaggy becomes less conspicuous and the image quality is enhanced.
As is understood from FIG. 1C, too, the pulse start positions at a left-hand inclined portion of the character xe2x80x9cAxe2x80x9d are smoothed by right-side pixels, and the pulse start positions at a right-hand inclined portion thereof are smoothed by left-side pixels.
Although FIG. 1C shows the example of 4-division, if an 8-division pulse width modulation is performed, nine kinds of pixels, i.e. 0/8, 1/8, 2/8, 3/8, 4/8, 5/8, 6/8, 7/8 and 8/8, can be generated (16 kinds if the pulse start position control is considered). The greater the division number, the larger the kinds of pixels to be generated. A higher image quality can thus be obtained.
The pulse width modulation has been performed, as described above, in order to enhance the image quality. For this purpose, in the prior art, pulse width modulation circuits using PLLs have been used, and n-division pulse width modulation signals have been generated.
Where a PLL is used, however, if an 8-division pulse width modulation is to be performed in a digital copying machine which operates with an NMHz (N=a given integer) image transfer clock, as shown in FIG. 3, it is necessary to use a 3.5-multiplication PLL. That is, a high-speed PLL input clock of (3.5xc3x97N) MHz is required.
For example, in a digital copying machine operating with a 60 MHz (N=60) image transfer clock, a 210 MHz PLL input clock is required. In the case of a pulse width modulating circuit requiring a pulse width modulation signal with a smaller pulse width, the image transfer clock frequency is limited and hardly feasible.
Specifically, if the division number is increased from 8-division to 16-division or 32-division in order to enhance the image quality, an image transfer clock twice or four times as high as the clock for the 8-division is required, and this is hardly feasible (as of September 1999, process: 0.35 xcexcm, C-MOS).
Furthermore, where a pulse width modulation circuit is to be realized in a wide-band frequency range, a plurality of PLLs are required and this increase the scale of the circuit. As regards the cost, the PLLs need to be incorporated in the circuit (plural PLLs being required to cover a wide band) and this increases the cost. The pulse width modulation circuit using a PLL has problems in various aspects.
Besides, in the conventional pulse width modulation system, information from the pulse width modulation circuit, for example, a signal indicating whether a modulated pulse width has a desired division number, is not transmitted to the CPU or microcomputer. Consequently, a variance in the pulse width modulation circuit due to an ambient variation such as temperature or supply voltage cannot be detected.
The object of the present invention is to provide a pulse width modulation system capable of realizing a pulse width modulation circuit with an inexpensive structure matching with modern higher-speed image transfer clocks and realizing a high-precision pulse width modulation coping with an ambient variation by a communication control with a CPU or a microcomputer, and an image forming apparatus having the pulse width modulation system and forming images.
In order to achieve this object, according to the present invention, there is provided a pulse width modulation system comprising a pulse width modulation circuit for outputting a necessary pulse width modulation signal in response to an input signal, and control means for controlling the pulse width modulation circuit, wherein the control means has means for outputting a delay setting signal and a division number setting signal to the pulse width modulation circuit in accordance with a phase comparison result signal output from the pulse width modulation circuit, and the pulse width modulation circuit comprises: switch control means for executing a control to generate a clock start signal, an EVEN-side data signal, an ODD-side data signal, an EVEN-side pulse start position signal, an ODD-side pulse start position signal and an EVEN/ODD switch signal, on the basis of a clock signal, a data signal and a pulse start position signal which are input; delay setting means for providing predetermined amounts of delay to the clock start signal from the switch control means, on the basis of the delay setting signal from the control means, and generating a plurality of pulse width modulation signals; phase select means for selecting one of the plurality of pulse width modulation signals generated by the delay setting means, on the basis of the division number setting signal from the control means, and outputting the selected signal as a clock end signal; comparison means for comparing the clock end signal from the phase select means with the clock start signal and outputting the phase comparison result signal to the control means; first select means for selecting an EVEN-side pulse width modulation signal candidate from the plurality of pulse width modulation signals generated from the delay setting means, on the basis of the EVEN-side data signal and the EVEN-side pulse start position signal generated from the switch control means; second select means, provided in parallel to the first select means, for selecting an ODD-side pulse width modulation signal candidate from the plurality of pulse width modulation signals generated from the delay setting means, on the basis of the ODD-side data signal and the ODD-side pulse start position signal generated from the switch control means; and switch means for receiving the EVEN-side pulse width modulation signal candidate selected by the first select means and the ODD-side pulse width modulation signal candidate selected by the second select means, selecting either the EVEN-side pulse width modulation signal candidate or the ODD-side pulse width modulation signal candidate in accordance with the EVEN/ODD switch signal from the switch control means, and outputting the selected candidate as the pulse width modulation signal.
There is also provided a pulse width modulation system comprising a pulse width modulation circuit for outputting a necessary pulse width modulation signal in response to an input signal, and control means for controlling the pulse width modulation circuit, wherein the control means has means for outputting a delay setting signal and a division number setting signal to the pulse width modulation circuit in accordance with a phase comparison result signal output from the pulse width modulation circuit, and the pulse width modulation circuit comprises: switch control means for executing a control to generate a clock start signal and an EVEN/ODD switch signal, on the basis of an input clock signal; delay setting means for providing predetermined amounts of delay to the clock start signal from the switch control means, on the basis of the delay setting signal from the control means, and generating a plurality of pulse width modulation signals; phase select means for selecting one of the plurality of pulse width modulation signals generated by the delay setting means, on the basis of the division number setting signal from the control means, and outputting the selected-signal as a clock end signal; comparison means for comparing the clock end signal from the phase select means with the clock start signal and outputting the phase comparison result signal to the control means; select means for selecting a pulse width modulation signal candidate from the plurality of pulse width modulation signals generated from the delay setting means, on the basis of the data signal and the pulse start position signal which have been input; inverting means for inverting a polarity of the pulse width modulation signal candidate selected by the select means; and switch means for receiving the pulse width modulation signal candidate inverted by the inverting means and the pulse width modulation signal candidate selected by the second select means, selecting either the pulse width modulation signal candidate inverted by the inverting means or the pulse width modulation signal candidate selected by the second select means in accordance with the EVEN/ODD switch signal from the switch control means, and outputting the selected candidate as the pulse width modulation signal.
There is also provided an image forming apparatus comprising: pulse width modulation means for outputting a necessary pulse width modulation signal in response to an input signal; image forming means for forming an image on an image formation medium on the basis of the pulse width modulation signal output from the pulse width modulation means; control means for controlling a pulse width modulation of the pulse width modulation means by detecting delay variation characteristics of the pulse width modulation means; and execution means for executing a control by the control means at a time of a predetermined operation.